This invention relates to a semiconductor device and, in particular, to a semiconductor device in which a double refresh operation mode is changed with reference to an internally-generated power supply voltage VPP (hereinafter will simply be referred to as a power supply voltage VPP) a power supply voltage level upon refreshing and relieving a memory cell.
As a semiconductor device, a dynamic random access memory (hereinafter referred to as “DRAM”) having a large capacity and randomly accessible is known. The DRAM holds memory information as electric charges stored in capacitors of memory cells. It is therefore required to perform a refresh operation by reading the memory information before the electric charges fade away, amplifying the memory information, and restoring the memory information into its original state. The electric charges stored in the capacitors of the memory cells in the DRAM fade away after lapse of certain time periods which may be called information holding times or retention times. The retention times are different from cell to cell and are not constant.
The retention times are continuously distributed from a short retention time to a long retention time. This is mainly because the electric charges as “HIGH level” written in the memory cells fade away due to junction leakage. The retention times are also affected by surface leakage and relationships with adjacent cells. In the DRAM, the retention times are long in most of the memory cells and are short in only a part of the memory cells. Those cells having short retention times are replaced by redundant memory cells to be relieved. However, due to the limitation in number of redundant circuits (that is, the redundant memory cells), some of the memory cells having short retention times may be kept present without being relieved.
In presence of the memory cells having short retention times, the semiconductor device is rejected as a defective product below standard. This results in a low production yield and a high production cost. In view of the above, proposal is made of a technique of relieving all memory cells having short retention times by providing a large number of redundant circuits. However, in case where a large number of redundant circuits are provided, the semiconductor device is inevitably increased in chip area. After all, the production cost is increased.
In order to overcome the above-mentioned problems, several techniques have been proposed as will presently be described. According to these techniques, the memory cells having short retention times are refreshed in a short cycle so as to be relieved without being replaced by the redundant circuits. For example, Japanese Unexamined Patent Application Publication (JP-A) No. H4-10297 discloses a semiconductor device in which particular cells having short retention times are refreshed more frequently as compared with other cells. Japanese Unexamined Patent Application Publication (JP-A) No. H08-306184 discloses a semiconductor device in which a fuse circuit group memorizes addresses of memory cells having short retention times. Each memory cell is refreshed in a long cycle or a short cycle depending upon its retention time. For those memory cells specified to have long retention times, a short-cycle refresh operation is skipped. Thus, a short-cycle or a long-cycle refresh operation is performed in accordance with fuse circuit information.
Japanese Unexamined Patent Application Publication (JP-A) No. 2005-116106 discloses double refresh as means for relieving the memory cells having short data retention times. Referring to FIGS. 1A and 1B, the double refresh will be described. In the double refresh, two word lines are activated and refreshed by one refresh command. For example. it is assumed that a refresh command is supplied at a time instant T0 to refresh a word line “0000”. In this event, judgment is made about whether or not a pair word line “1000” paired with the word line “0000” has a short data retention time (i.e., the pair word line “1000” is connected to an array containing a memory cell having a short data retention time). If it is judged that the pair word line “1000” has a short data retention time, the word line “0000” and the pair word line “1000” are simultaneously activated and refreshed.
The pair word line “1000” is refreshed twice, i.e., when the word line “0000” is refreshed and when the pair word line “1000” itself is refreshed. Therefore, the pair word line “1000” having a short data retention time is refreshed in a short cycle which corresponds to a half of a normal refresh cycle. The pair word line “1000” having a short data retention time is relieved by being refreshed in a short refresh cycle. In the following description, a row address “0000” and the word line “0000” will be understood to have the same meaning because the word line is selected by the row address.
As the double refresh, a time-division double refresh operation mode shown in FIG. 1A is known. In the time-division double refresh operation mode, a refresh cycle is time-divided into a first half and a second half as timings at which two word lines are activated upon carrying out the double refresh. Further, a parallel double refresh operation mode shown in FIG. 1B is known. In the parallel double refresh operation mode, two word lines are simultaneously activated in the refresh cycle upon carrying out the double refresh. In case where the pair word line has a data retention time longer than a normal data retention time, the pair word line is not refreshed. One of the above-mentioned double refresh operation modes is preliminarily selected as a desired operation mode at a design stage or upon wafer delivery.
In the above-mentioned double refresh operation modes, the two word lines are activated in one refresh cycle. It is further assumed that two adjacent word lines have short data retention times. In this event, it is necessary to increase a supply capacity of a VPP power supply circuit for generating a power supply voltage VPP, which is generated in the semiconductor device by stepping up an external supply voltage and supplied to the word lines, to a level twice that required in a normal refresh operation. Accordingly, the VPP power supply circuit is inevitably increased in area. This results in an increase in chip cost.
As described above, the semiconductor device has a problem that, because of presence of the memory cells having short retention times, the yield is decreased. In case where the double refresh is applied, the power supply voltage is significantly lowered inside a chip and the VPP power supply circuit requires an area twice that required in the normal refresh operation. This results in an increase in chip cost.